Compression ratio improvement by lazy match evaluation on the string search cam

ABSTRACT

A plurality of stored data sequences that match one or more search data sequences are determined. Each of the stored data sequences of the plurality of stored data sequences comprise a plurality of data elements and the stored data sequences are stored in a content addressable memory array. A longest stored data sequence of the plurality of stored data sequences is determined using a plurality of tracing circuits. An address associated with the longest stored data sequence of the plurality of stored data sequences is determined. A count of data elements of the longest stored data sequence of the plurality of stored data sequences is determined.

TECHNICAL FIELD

The present inventive subject matter relates to computing systems. Inparticular, it relates to using computing hardware to improve acompression ratio.

BACKGROUND

The deflate compression (RFC1951) is a compression algorithm on whichZLIB (RFC1950) and GZIP (RFC1952) widely used in computers are based.The deflate compression is a combination of two kinds of compressionalgorithms, and LZ77 encoding is used in the first half of the deflatecompression. The LZ77 encoding is to compress data by searching for aniterative character sequence part of the data and replacing theiterative character sequence part with the position and length of theiterative character sequence part. For example, in LZ77 encoding of acharacter sequence “IBM is IBM”, the “IBM” that occurs the second timeis an iterative character sequence part and therefore is compressed.More specifically, the iterative character sequence part is replacedwith a code, such as “7, 3” indicating that a character sequence havinga length of three characters starting with the seventh character priorto the leading character of the iterative character sequence part, andthus is compressed. In this case, the greater the length of theiterative part, the higher the compression ratio is.

According to the specifications of the deflate compression, up to 32kilobytes of preceding data is searched for an iterative charactersequence part, and the search for an iterative character sequence partuses a large amount of character sequence comparison processing.

If the processing is performed by software, the processing can take along time. Typically, software uses the hash method to reduce the searchtime. However, if there are many character sequences having the samehash value, the hash method may discard some of the character sequences.Thus, it is difficult to completely search the whole of a character.

SUMMARY

The present inventive subject matter provides an apparatus thatdetermines a search start point in a first data element sequence insearching a second data element sequence based on the first data elementsequence, comprising: a content addressable memory that stores each dataelement of a plurality of data elements forming the second data elementsequence at an address corresponding to a position of the data elementin the second data element sequence, and outputs, when a search dataelement is given, the address at which a match data element that matcheswith the search data element is stored if the match data element isstored as one of the plurality of data elements; a plurality ofgenerating circuits each of which is a generating circuit that generatesrow presence information based on the address output from the contentaddressable memory if the search data element is given to the contentaddressable memory and a sequence of matching data elements that matcheswith a sequence starting at a specific start point determined for thegenerating circuit in a sequence of previously given search dataelements is stored in the content addressable memory, the row presenceinformation indicating that the sequence of matching data elements isstored; and a determining part that determines the search start pointbased on a plurality of pieces of row presence information successivelygenerated by the plurality of generating circuits when the data elementsforming the first data element sequence are successively given to thecontent addressable memory as the search data element.

If the number of successive generations of the row presence informationby a particular generating circuit of the plurality of generatingcircuits satisfies a predetermined condition for the number to berecognized to be large enough, the determining part may determine thespecific start point determined for the particular generating circuit asthe search start point.

The predetermined condition may include a condition that the number ofsuccessive generations of the row presence information by the particulargenerating circuit is greater than the number of successive generationsof the row presence information by any other generating circuit of theplurality of generating circuits.

Furthermore, the present inventive subject matter provides an apparatusthat compresses a data element sequence by replacing a first partialdata element sequence of the data element sequence with information on aposition and a length of a second partial data element sequence of thedata element sequence, comprising: a content addressable memory thatstores each data element of a plurality of data elements forming atleast a part of the data element sequence at an address corresponding toa position of the data element in the data element sequence, andoutputs, when a search data element is given, the address at which amatch data element that matches with the search data element is storedif the match data element is stored as one of the plurality of dataelements; a plurality of generating circuits each of which is agenerating circuit that generates row presence information and rowaddress information based on the address output from the contentaddressable memory if the search data element is given to the contentaddressable memory and a sequence of matching data elements that matcheswith a sequence starting at a specific start point determined for thegenerating circuit in a sequence of previously given search dataelements is stored in the content addressable memory, the row presenceinformation indicating that the sequence of matching data elements isstored, and the row address information indicating the address at whichthe sequence of matching data elements is stored; and a determining partthat determines a position and a length of the second partial dataelement sequence based on a plurality of pieces of row presenceinformation and a plurality of pieces of row address informationsuccessively generated by the plurality of generating circuits bysuccessively giving the data elements forming the first partial dataelement sequence to the content addressable memory as the search dataelement.

Furthermore, the present inventive subject matter provides an apparatusthat compresses a data element sequence by replacing a first partialdata element sequence of the data element sequence with information on aposition and a length of a second partial data element sequence of thedata element sequence, comprising: a content addressable memory thatstores each data element of a plurality of data elements forming atleast a part of the data element sequence at an address corresponding toa position of the data element in the data element sequence, andoutputs, when a search data element is given, the address at which amatch data element that matches with the search data element is storedif the match data element is stored as one of the plurality of dataelements; a primary generating circuit that generates first row presenceinformation and first row address information based on the addressoutput from the content addressable memory if the search data element isgiven to the content addressable memory and a sequence of matching dataelements that matches with a sequence starting at a reference dataelement in a sequence of previously given search data elements is storedin the content addressable memory, the first row presence informationindicating that the sequence of matching data elements is stored, andthe first row address information indicating the address at which thesequence of matching data elements is stored; K expansion generatingcircuits a J-th expansion generating circuit of which generates firstrow presence information and first row address information based on theaddress output from the content addressable memory if the search dataelement is given to the content addressable memory and a sequence ofmatching data elements that matches with a sequence starting at a J-thdata element from the reference data element in a sequence of previouslygiven search data elements is stored in the content addressable memory,the first row presence information indicating that the sequence ofmatching data elements is stored, and the first row address informationindicating the address at which the sequence of matching data elementsis stored (K represents a natural number, and J represents a naturalnumber equal to or smaller than K); a first outputting circuit thatoutputs second row presence information if the search data element isgiven to the content addressable memory and the first row presenceinformation is generated by any of the primary generating circuit andthe K expansion generating circuits, the second row presence informationindicating that a sequence of matching data elements that matches with asequence starting at any data element subsequent to the reference dataelement in a sequence of previously given search data elements is storedin the content addressable memory; a second outputting circuit thatoutputs, as second row address information, the first row addressinformation generated by at least one generating circuit that generatesthe first row presence information of the primary generating circuit andthe K expansion generating circuits if the search data element is givento the content addressable memory; and a determining part thatsuccessively gives the data elements forming the first partial dataelement sequence to the content addressable memory as the search dataelement, determines the position of the second partial data elementsequence based on the second row address information output from thesecond outputting circuit immediately before the first outputtingcircuit no longer outputs the second row presence information, anddetermines the length of the second partial data element sequence basedon the number of successive outputs of the second row presenceinformation from the first outputting circuit.

Furthermore, the present inventive subject matter provides a method ofdetermining a search start point in a first data element sequence insearching a second data element sequence based on the first data elementsequence, comprising: a content addressable memory that stores each dataelement of a plurality of data elements forming the second data elementsequence at an address corresponding to a position of the data elementin the second data element sequence, and outputs, when a search dataelement is given, the address at which a match data element that matcheswith the search data element is stored if the match data element isstored as one of the plurality of data elements; a step of eachgenerating circuit of a plurality of generating circuits generating rowpresence information based on the address output from the contentaddressable memory if the search data element is given to the contentaddressable memory and a sequence of matching data elements that matcheswith a sequence starting at a specific start point determined for thegenerating circuit in a sequence of previously given search dataelements is stored in the content addressable memory, the row presenceinformation indicating that the sequence of matching data elements isstored; and a step of determining the search start point based on aplurality of pieces of row presence information successively generatedby the plurality of generating circuits by successively giving the dataelements forming the first data element sequence to the contentaddressable memory as the search data element.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing an example of a configuration of amicrocomputer to which an embodiment of the present inventive subjectmatter is applied;

FIG. 2 is a block diagram showing an example of a configuration of aniterative data searching circuit according to the embodiment of thepresent inventive subject matter;

FIG. 3 is a circuit diagram showing an example of a configuration of acontent addressable memory;

FIG. 4 is a block diagram showing an example of a configuration of acomparison result controlling circuit according to the embodiment of thepresent inventive subject matter;

FIGS. 5( a) to 5(e) are conceptual diagrams for illustrating anoperation of the comparison result controlling circuit according to theembodiment;

FIG. 6 is a diagram showing a specific example of a character sequencesearch in which a plurality of character sequence tracings needs to beperformed in parallel;

FIG. 7-1 is a diagram showing an example of a configuration of aniterative data searching apparatus according to the embodiment of thepresent inventive subject matter;

FIG. 7-2 is a diagram showing the example of the configuration of theiterative data searching apparatus according to the embodiment of thepresent inventive subject matter;

FIGS. 8-1( a) and 8-1(b) are conceptual diagrams for illustratingoperations in the iterative data searching circuit and a tracing circuitaccording to the embodiment of the present inventive subject matter;

FIGS. 8-2( c) and 8-2(d) are conceptual diagrams for illustratingoperations in the iterative data searching circuit and the tracingcircuit according to the embodiment of the present inventive subjectmatter;

FIGS. 8-3( e) and 8-3(f) are conceptual diagrams for illustratingoperations in the iterative data searching circuit and the tracingcircuit according to the embodiment of the present inventive subjectmatter;

FIG. 9 is a flowchart showing an example of an operation of a datacompression controller according to the embodiment of the presentinventive subject matter; and

FIG. 10 is a flowchart showing details of a compressed data outputprocessing in the flowchart shown in FIG. 9.

DESCRIPTION OF EMBODIMENT(S)

In the following, an embodiment of the present inventive subject matterwill be described in detail with reference to the accompanying drawings.

FIG. 1 shows a configuration of a part of a microcomputer 10 to whichthis embodiment is applied. The microcomputer 10 includes a CPU 12, aROM 14 and a RAM 16, which are connected to each other by a bus 18,which includes an address bus, a data bus, a control bus and the like.

The microcomputer 10 further includes a plurality of iterative datasearching apparatuses 20 a, 20 b and so on according to this embodiment,which are connected to the bus 18 via a data compression controller 22that controls the operation of the iterative data searching apparatuses.The iterative data searching apparatuses 20 a, 20 b and so on have thesame configuration, and P+1 iterative data searching apparatuses areprovided in this embodiment. In the following, the P+1 iterative datasearching apparatuses will be collectively referred to as an “iterativedata searching apparatus 20”, and a configuration of the iterative datasearching apparatus 20 will be described. Each individual iterative datasearching apparatus will be referred to as a block, such as a “block 0”and a “block P”, to distinguish it from the other iterative datasearching apparatuses.

FIG. 2 is a diagram showing an iterative data searching circuit 21 onwhich the iterative data searching apparatus 20 according to thisembodiment is based.

The iterative data searching circuit 21 has a CAM cell array 26comprising a large number of content addressable memory cells 28arranged in a matrix (the content addressable memory will be abbreviatedas CAM hereinafter). In the drawing, the CAM cells 28 are shown bycircles. In the CAM cell array 26, N+1 word lines WL0 to WLN, N+1 matchlines MATCH0 to MATCHN and M+1 bit line pairs BL0 and BL0′ to BLM andBLM′ are each arranged in a matrix, and each CAM cell 28 is connected toany of the word lines WL0 to WLN, any of the match lines MATCH0 toMATCHN and any of the bit line pairs BL0 and BL0′ to BLM and BLM′.

As shown in FIG. 3, the CAM cell 28 has two NOT circuits 30 and 32 withan input terminal and an output terminal of one circuit connected to anoutput terminal and an input terminal of the other circuit,respectively. The loop formed by the NOT circuits 30 and 32 forms astorage circuit (of SRAM type) that stores 1-bit data. The outputterminal of the NOT circuit 30 is connected to the source of an N-MOSFET34, the output terminal of the NOT circuit 32 is connected to the sourceof an N-MOSFET 36, and the gates of the N-MOSFETs 34 and 36 areconnected to the word line WL. The drains of the N-MOSFETs 34 and 36 areconnected to the bit lines BL and BL′, respectively.

To write 1-bit data to the CAM cell 28, the word line WL is set at HIGHlevel, the bit line BL is set at a level corresponding to data D to bewritten (HIGH level if the data D is “1”, and LOW level if the data is“0”), and the bit line BL′ is set at a level inverted from the level ofthe bit line BL (LOW level if the bit line BL is at HIGH level, and HIGHlevel if the bit line BL is at LOW level). This causes the N-MOSFETs 34and 36 to turn on, and thus, the data supplied via the bit lines BL andBL′ is held in the loop of the NOT circuits 30 and 32.

The output terminal of the NOT circuit 30 is connected to the gate ofthe N-MOSFET 38, and the output terminal of the NOT circuit 32 isconnected to the gate of the N-MOSFET 40. The NOT circuit 32 outputsdata (Q′) inverted from the data D, and the NOT circuit 30 outputs dataQ (=D) inverted from the data Q′. The drains of the N-MOSFETs 38 and 40are connected to the bit lines BL′ and BL, respectively, and the sourcesof the N-MOSFETs 38 and 40 are connected to the gate of an N-MOSFET 42.The drain of the N-MOSFET 42 is connected to the match line MATCH, andthe source of the N-MOSFET 42 is grounded.

In this embodiment, as an example, M+1 CAM cells 28 are connected to thesame word line and the same match line, so that M+1-bits of data can bestored in the plurality of CAM cells 28 connected to the same word lineand the same match line (these CAM cells will be referred to as a CAMcell row hereinafter). In the CAM cell array 26, an address is allocatedto each CAM cell row.

Referring to FIG. 2 again, the iterative data searching circuit 21 has atiming controller 50. The timing controller 50 is connected to the datacompression controller 22. When a search instruction SEARCH is inputfrom the data compression controller 22 to the timing controller 50, theiterative data searching circuit 21 performs a “search,” which involvesrepeatedly comparing input search data with data stored in each CAM cellrow of the CAM cell array 26 and writing the search data to any of theCAM cell rows of the CAM cell array 26.

A system clock CLOCK is input from the data compression controller 22 tothe timing controller 50, and the timing controller 50 generates andoutputs a clock SR synchronized with the system clock CLOCK. The clockSR is also output to a write buffer 56 connected to the timingcontroller 50.

The write buffer 56 is connected to the data compression controller 22,and search data is successively input to the write buffer 56 from thecontroller 22. The write buffer 56 is connected to the bit line pairsBL0 and BL0′ to BLM and BLM′, holds the input search data, and changesthe level of the bit line pairs BL0 and BL0′ to BLM and BLM′ (that is,drives the bit line pairs) according to the value of the held searchdata at a at a timing synchronized with the clock SR input from thetiming controller 50. While the write buffer 56 is driving the bit linepairs according to predetermined search data, the predetermined searchdata is compared with the data stored in each CAM cell row and writtento a predetermined CAM cell row.

The timing controller 50 is also connected to an address decoder 52, andthe clock SR is also output to the address decoder 52. The addressdecoder 52 is connected to the data compression controller 22, and thedata compression controller 22 designates the address of the CAM cellrow to which the search data is to be written (a write address WADR).The word lines WL0 to WLN are connected to the address decoder 52, andthe address decoder 52 asserts (enables) the word line of the CAM cellrow corresponding to the designated write address WADR and writes thepredetermined search data to the CAM cell row corresponding to thedesignated address at a timing synchronized with the clock SR. Morespecifically, the predetermined search data is written to the CAM cellrow corresponding to the designated address after comparison of thepredetermined search data with the data stored in each CAM cell rowduring a period in which the write buffer 56 is driving the bit linepairs according to the predetermined search data.

N+1 match line controllers 58 ₀ to 58 _(N), each of which is connectedto the corresponding one of the match lines MATCH0 to MATCHN, is alsoconnected to the timing controller 50, and the clock SR is also outputto the match line controllers 58 ₀ to 58 _(N). Based on the input clockSR, the match line controllers 58 ₀ to 58 _(N) charge (precharge) thematch lines MATCH0 to MATCHN to HIGH level before the search data iscompared with the data stored in each CAM cell row. The precharging ofthe match lines by the match line controllers 58 ₀ to 58 _(N) occurs ina period after driving of the bit line pairs according to thepredetermined search data by the write buffer 56 is completed and beforedriving of the bit line pairs according to the next search data isstarted.

The match lines MATCH0 to MATCHN are also connected to a comparisonresult controlling circuit 60. As shown in FIG. 4, the comparison resultcontrolling circuit 60 has latches 62 ₀ to 62 _(N), signal generatingcircuits 64 ₀ to 64 _(N) and latches 66 ₀ to latches 66 ₀ to 66 _(N). InFIG. 4, illustration of the match line controllers 58 ₀ to 58 _(N) isomitted. Of the signal generating circuits 64 ₀ to 64 _(N), althoughFIG. 4 shows only a specific configuration of the signal generatingcircuit 64 ₁ connected to the match line MATCH1, the other signalgenerating circuits may have the same configuration. In the following,only a circuit part of the comparison result controlling circuit 60involved with the match line MATCH1 will be described.

The match line MATCH1 is connected to an input terminal of the latch 62₁, and an output terminal of the latch 62 ₁ is connected to one of twoinput terminals of each of AND circuits 68 ₁ and 70 ₁ in the signalgenerating circuit 64 ₁. To the other of the two input terminals of theAND circuit 68 ₁, an output terminal of an OR circuit 72 ₁ is connected.One of two input terminals of the OR circuit 72 ₁ and the other of thetwo input terminals of the AND circuit 70 ₁ are connected to an outputterminal of the latch 66 ₀ in the preceding stage. An output terminal ofthe AND circuit 68 ₁ is connected to an input terminal of the latch 66₁, and an output terminal of the latch 66 ₁ is connected to an inputterminal of each of an OR circuit 72 ₂ and an AND circuit 70 ₂ (neithershown) in the signal generating circuit 64 ₂ in the following stage, aswith the output terminal of the latch 66 ₀ described above. The outputterminal of the latch 66 ₁ is also connected to an input terminal of afirst priority encoder 74. An output terminal of the AND circuit 70 ₁ isconnected to one of input terminals of an OR circuit 78. To the otherinput terminals of the OR circuit 78, output terminals of AND circuits70 ₀ and 70 ₂ to 70 _(N) (not shown) are connected. An output terminalof the OR circuit 78 is connected to one of input terminals of an ORcircuit 80. To the other input terminals of the OR circuit 80, outputterminals of the OR circuits 78 in the other iterative data searchingcircuits 21 are connected. An output terminal of the OR circuit 80 isconnected to input terminals of OR circuits 72 ₀ to 72 _(N) in thesignal generating circuits 64 ₀ to 64 _(N) via an inverter, not shown(only the OR circuit 72 ₁ is shown in the drawing). A feedback signalORFB output from the OR circuit 80 is inverted and then input to the ORcircuits 72 ₀ to 72 _(N). The feedback signal ORFB output from the ORcircuit 80 is also output to the data compression controller 22 (seeFIG. 2).

FIG. 4 shows the comparison result controlling circuit 60 in theiterative data searching circuit 21 in the block 0, and one of the twoinput terminals of the OR circuit 72 ₀ in the signal generating circuit64 ₀ is connected to the output terminal of the latch 66 _(N) in thecomparison result controlling circuit 60 in the block P. The outputterminal of the latch 66 _(N) in the comparison result controllingcircuit 60 in the block 0 is connected to one of the two input terminalsof the OR circuit 72 ₀ in the comparison result controlling circuit 60in the block 1 (see FIG. 2).

An output terminal of the first priority encoder 74 is connected to aninput terminal of the second priority encoder 76. The first priorityencoder 74 encodes an address corresponding to a signal at HIGH levelafter a “search” operation of the signals input from the latches 66 ₀ to66 _(N) in the comparison result controlling circuit 60 and outputs theencoded address as a match address MADR0 to the second priority encoder76, and outputs a logical sum of the signals input from the latches 66 ₀to 66 _(N) as a match signal MSIG0 to the second priority encoder 76. Ifa plurality of signals of the signals input from the latches 66 ₀ to 66_(N) are at HIGH level, an address of the content addressable memorycell row of the highest priority according to a predetermined criterion,for example, the lowest address or the address closest to the writeaddress WADR at that point in time, is output as the match addressMADR0. The reason why the latter address is output is because distanceinformation used in compression has a small volume and therefore leadsto a high compressibility.

To the input terminal of the second priority encoder 76, the matchaddresses MADR and the match signals MSIG output from the first priorityencoders 74 in the other iterative data searching circuits 21 are alsoinput. An output terminal of the second priority encoder 76 is connectedto the data compression controller 22.

The second priority encoder 76 has substantially the same configurationas the first priority encoder 74. The second priority encoder 76 outputsan address of the highest priority according to a predeterminedcriterion among the addresses for which the match signals MSIG0 to MSIGPare at HIGH level among the addresses MADR0 to MADRP input from theplurality of first priority encoders 74, for example, an address formedby adding the address of the relevant block (the address allocated tothe relevant one of the plurality of iterative data searchingapparatuses) to the lowest address or the address closest to the writeaddress WADR at that point in time, as the match address MADR to thedata compression controller 22, and outputs a signal indicating alogical sum of the match signals MSIG0 to MSIGP input from the pluralityof first priority encoders 74 as the match signal MSIG to the datacompression controller 22.

Next, as an effect of this embodiment, a comparison operation thatoccurs in the iterative data searching circuit 21 will be described. Tocompress data to be compressed (original data), the data compressioncontroller 22 successively extracts unit data having a predetermined bitlength from the original data as search data and successively outputsthe search data to the iterative data searching circuit 21 along withthe search instruction SEARCH and the write address WADR, as describedlater.

In the iterative data searching circuit 21 having received the searchinstruction SEARCH, the timing controller 50 outputs the clock SR to thewrite buffer 56, the address decoder 52 and the match line controllers58 ₀ to 58 _(N), the match line controller 58 precharges the match linesMATCH0 to MATCHN before the comparison operation by the CAM cell array26, and the write buffer 56 holds the input search data and drives thebit line pairs BL0 and BL0′ to BLM and BLM′ according to the searchdata.

In each CAM cell 28 in the CAM cell array 26, the N-MOSFET 38 is turnedon if the data Q output from the NOT circuit 30 is “1” (HIGH level), andthe N-MOSFET 40 is turned on if the data Q′ output from the NOT circuit32 is “1”. Therefore, if the data Q (Q′) held in the loop of the NOTcircuits 30 and 32 matches with the data D (D′) supplied through the bitline pairs BL and BL′, the N-MOSFET 42 is not turned on. And if the dataQ (Q′) does not match with the data D (D′), a current flows from thedrain to the source of either of the N-MOSFETs 38 and 40 that is turnedon, and the N-MOSFET 42 is turned on. As a result, the level of theprecharged match line MATCH is reduced to LOW level (discharge).

The data comparison described above simultaneously occurs in the CAMcells 28. A plurality of CAM cells 28 (a CAM cell row) is connected toone match line MATCH, and the comparison operation between the inputcharacter data and the character data stored in the CAM cell row isgenerally completed in the first half of one period of the clock SR.Each match line is maintained at HIGH level only if the N-MOSFET 42 isnot turned on in all the CAM cell 28 connected thereto, that is, if thecharacter data stored in the CAM cell row matches with the characterdata input to the write buffer 56, and is set at LOW level if thecharacter data do not match with each other.

In the second half of one period of the clock SR, the address decoder 52asserts (enables) the word line of the CAM cell row corresponding to theinput write address WADR, and the search data is written to the CAM cellrow. Then, when writing of the search data to the CAM cell row iscompleted, the word line is set at LOW level, and driving of each bitline pair by the write buffer 56 is stopped, the match line controller58 precharges each match line again.

The operation (comparison operation) described above occurs in oneperiod of the clock SR and is repeated in synchronization with input ofthe search data, the search instruction SEARCH and the write addressWADR from the data compression controller 22.

The character data in the above description is an example of dataelement. The feedback signal ORFB set at “1” is an example of rowpresence information that indicates that a row of matching data elementsis stored, that is, first row presence information. The match addressMADR is an example of row address information that indicates the addressat which the row of matching data elements is stored, that is, first rowaddress information. The part formed by the signal generating circuit64, the latch 66, the first priority encoder 74, the second priorityencoder 76 and the OR circuit 78 is an example of a generating circuit,in particular, a primary generating circuit. Furthermore, the datacompression controller 22 is an example of a determining part thatdetermines the search start point and the position and length of thedata element row.

Next, an operation of the comparison result controlling circuit 60 willbe described with reference to FIG. 5. As an example, FIG. 5 shows acase where the original data is text data, a character data sequence“ABABBC” is previously stored in CAM cell rows of addresses “0” to “5”,and character data A, B, B, B, C and so on are input in this order asthe search data. The latches 62 ₀ to 62 ₅ are shown as ML0 to ML5, andthe latches 66 ₀ to 66 ₅ are shown as PS0 to PS5. In the followingdescription, it will be assumed that the result of the comparisonoperation in the other iterative data searching apparatuses isconstantly “not match”.

As shown in FIG. 5( a), when character data “A” is first input as thesearch data, the comparison result is “match” in the CAM cell rows ofaddresses “0” and “2” (enclosed by the thick frame in FIG. 5). Of thematch lines MATCH0 to MATCH5, the match lines other than the match linesMATCH0 and MATCH2 are discharged to LOW level, and only the match linesMATCH0 and MATCH2 are maintained at HIGH level. The levels of the matchlines MATCH0 to MATCH5 are held in the latches ML0 to ML5 in thecomparison result controlling circuit 60, respectively, and then, in thenext period, output to the signal generating circuits 64 ₀ to 64 ₅,respectively.

As shown in FIG. 5( a), at this point in time, the levels held in thelatches PS0 to PS5 are LOW level (“0” in FIG. 5, the same holds true forthe latches PS6 to PSN, which are not shown, and the latches PS0 to PSNof the other blocks), and therefore, the signals output from the ANDcircuits 70 ₀ to 70 ₅ are all at LOW level, and the feedback signalORFB0 output from the OR circuit 78 and the feedback signal ORFB outputfrom the OR circuit 80 are also at LOW level. As can be seen from theabove description, according to this embodiment, the feedback signalORFB is not set at HIGH level when only one character matches with thestored data, that is, when only one comparison operation in a CAM cellrow yields a comparison result “match”. Since the feedback signal ORFBis at LOW level, the outputs of the OR circuits 72 ₀ to 72 ₅ are all atHIGH level, and the levels of the signals output from the latches ML0 toML5 are held in the latches PS0 to PS5 without change (see FIG. 5( b)).

As shown in FIG. 5( b), when character data “B” is input as the nextsearch data, the comparison result is “match” in the CAM cell rows ofaddresses “1”, “3” and “4”, and the levels of the match lines (only thematch lines MATCH1, MATCH3 and MATCH5 are at HIGH level) are held in thelatches ML0 to ML5. Then, in the next period, the outputs of the latchesML1, ML3 and ML5 are set at HIGH level, and the outputs of the latchesPS0 and PS2 (that is, the latches PS in the respective preceding stagesof the latches ML1 and ML3) are set at HIGH level, so that the signalsoutput from the AND circuits 70 ₁ and 70 ₃ are set at HIGH level, andthe feedback signal ORFB0 output from the OR circuit 78 and the feedbacksignal ORFB output from the OR circuit 80 are set at HIGH level, asshown in FIG. 5( b).

As can be seen from the above description, the feedback signal ORFB isset at high level only if two or more successive characters match withthe stored data, that is, if a data sequence comprising a plurality ofsuccessively input pieces of search data is already stored in the CAMcell array 26. If it is assumed that the first priority encoder 74outputs the lowest address as the match address MADR0, the match addressMADR0 is an address “0”, which corresponds to the latch PS0. Althoughthe match address MADR output from the second priority encoder 76depends on the value of the match addresses input from the otheriterative data searching apparatuses, the values of lower significancebits of the match address MADR are equal to the values of the matchaddress MADR0 if the data does not match with the stored data in theother iterative data searching apparatuses. The values of highersignificance bits of the match address MADR are the value of the addressof the matching encoder block (the address allocated to the relevant oneof the plurality of iterative data searching apparatuses). In this case,since the relevant block is the block of the address “0”, the values areall 0.

As shown in FIG. 5( c), when character data “B” is input as the nextsearch data, the same match lines as those in the case of the precedingsearch data are set at HIGH level, and the levels of the match lines areheld in the latches ML0 to ML5 and then output to the signal generatingcircuits 64 ₀ to 64 ₅. At this point in time, of the latches ML1, ML3and ML4 whose outputs are at HIGH level, only the latch ML4 receives anoutput at HIGH level from the latch PS in the preceding stage, so thatof the signals output from the AND circuits 70 ₁, 70 ₃ and 70 ₄, onlythe signal output from the AND circuit 70 ₄ is at HIGH level. Therefore,the feedback signal ORFB0 output from the OR circuit 78 is maintained atHIGH level, and the match address MADR0 is an address “4”, whichcorresponds to the latch PS4.

Since the feedback signal ORFB is maintained at HIGH level, provided thecurrent cycle is denoted by “m”, a signal corresponding to a logicalproduct of an output ML(n, m) of a latch ML of an address “n” and anoutput PS(n−1, m) of a latch PS in the preceding stage is output to alatch PS of an address “n”. As a result, only the latch PS4 holds HIGHlevel.

Then, as shown in FIG. 5( d), character data “B” is input as the nextsearch data. In this case, the levels of the match lines temporarilyheld in the latches ML0 to ML5 and then input to the signal generatingcircuits 64 ₀ to 64 ₅ are the same as those in the case of the precedingsearch data. However, all the latches ML1, ML3 and ML4 that outputsignals at HIGH level receive signals at LOW level output from thelatches PS in the respective preceding stages, so that the all thesignals output from the AND circuits 70 ₀ to 70 ₅ are at LOW level, andthe feedback signal ORFB0 and the feedback signal ORFB are at LOW level.When the feedback signal ORFB is set at LOW level, the output signals ofthe OR circuits 72 ₀ to 72 ₅ in the signal generating circuits 64 ₀ to64 ₅ are set at HIGH level, so that the levels of the signals outputfrom the latches ML1 to ML5 are held in the latches PS0 to PS5 withoutchange.

Then, as shown in FIG. 5( e), when character data “C” is input as thenext search data, only the match line MATCH5 is set at HIGH level, andthe levels of the match lines are temporarily held in the latches ML0 toML5 and then output to the signal generating circuits 64 ₀ to 64 ₅,respectively. In this case, only the latch ML5 outputs a signal at HIGHlevel, and the latch PS4 in the preceding stage also outputs a signal atHIGH level. As a result, of the signals output from the AND circuits 70₀ to 70 ₅, only the signal output from the AND circuit 70 ₅ is set atHIGH level. Therefore, the feedback signal ORFB0 output from the ORcircuit 78 is maintained at HIGH level, and the match address MADR0 isan address “1”, which corresponds to the latch PS1.

As described above, the iterative data searching circuit 21 has afunction of searching the whole of the CAM cell array 26 for a characterthat matches with every input character and a function of holdinginformation on whether the sequence of characters preceding anycharacter that matches with a character stored in the CAM cell array 26matches with a character sequence stored in the CAM cell array 26 andcan search for a character sequence at a much higher speed than othermethods.

There is a problem of how to start tracing of a character sequence.Typically, tracing of the character sequence starts at the position ofthe first matching character. According to this method, a charactersequence can be efficiently compressed to some extent. Depending on thecharacter sequence to be compressed, however, starting tracing acharacter sequence at a position of the first matching character may notlead to the best compression.

FIG. 6 shows an example of such a character sequence search.

In this example, as shown in FIG. 6( a), in a state where ten charactersstarting with “A” and ending with “Y” (enclosed by a frame) have beeninput, the character sequence consisting of ten characters is searchedfor a character sequence that matches with a newly input charactersequence “ABCDEF”.

If tracing is started at the first matching character, the compressionresult is as shown in FIG. 6( b). More specifically, a charactersequence that matches with a character sequence “ABC” (enclosed by athick frame) is first found, and then, a character sequence that matcheswith the remaining character sequence “DEF” of the newly input charactersequence (enclosed by a thick frame) is found. Thus, the charactersequence “ABCDEF” is compressed by being replaced with “<10, 3><7, 3>”.

However, if the first matching character is ignored, and tracing isstarted at the position of the second matching character, thecompression result is as shown in FIG. 6( c). That is, a charactersequence that matches with a character sequence “BCDEF” (enclosed by athick frame) is found. Thus, the character sequence “ABCDEF” is replacedwith “A<7, 5>”, and the compressibility is higher than that in the caseshown in FIG. 6( b).

Whether the first matching character should be ignored or how manymatching characters from the first matching character should be ignoreddepends on the attributes of the data to be compressed. Therefore, in apractical application, it is necessary to perform a plurality oftracings at the same time and select the tracing that yields the longestmatching character sequence by discarding the others that yield shortercharacter sequences.

To this end, according to this embodiment, the byte match detectingmechanism described above with reference to FIGS. 2 to 5 is used, and aplurality of character sequence tracing mechanisms are cascade-connectedto the mechanism. The plurality of character sequence tracing mechanismsefficiently perform a character sequence matching search in parallel,with the trace start points being shifted depending on the positions ofthe character sequence tracing mechanisms in the cascade, and select oneof the tracings that yields the longest matching character sequence. Inother words, the matching character detecting mechanism that occupies alarge area of the apparatus described above with reference to FIGS. 2 to5 is used, and only a plurality of character sequence tracing mechanismsare additionally provided. In this way, the increase of the hardwareresource is minimized, and the character sequence searching function isenhanced without reducing the throughput.

FIGS. 7-1 and 7-2 show an example of the configuration of the iterativedata searching apparatus 20 according to this embodiment.

As shown in FIG. 7-1, the iterative data searching apparatus 20 includesthe iterative data searching circuit 21 and tracing circuits 100 ₁, 100₂, . . . , and 100 _(K).

The internal configuration of the iterative data searching circuit 21 isthe same as that described above with reference to FIGS. 2 to 4.However, because of the tracing circuits 100 ₁, 100 ₂, . . . , and 100_(K) connected thereto, the configuration of the part of the iterativedata searching circuit 21 that receives signals from and outputs signalsto external circuits slightly differs from that described above withreference to FIGS. 2 to 5, and only the part will be described below. Inthe drawings, the latches 62 ₀ to 62 _(N) in FIG. 4 are collectivelyshown as the latch 62, and the latches 66 ₀ to 66 _(N) in FIG. 4 arecollectively shown as the latch 66. As in FIG. 4, only the AND circuit68 _(k), the AND circuit 70 ₁ and the OR circuit 72 ₁ of the ANDcircuits 68 ₀ to 68 _(N), the AND circuits 70 ₀ to 70 _(N) and the ORcircuit 72 ₀ to 72 _(N) are shown. Note that the subscripts are notshown.

As shown in FIG. 7-1, the iterative data searching circuit 21 furtherincludes the OR circuit 78 and a JK flip-flop 102 ₁. An output terminalof the OR circuit 78 is connected to one of input terminals of an ORcircuit 84, and an output terminal of the OR circuit 84 is connected toone of the two input terminals of the OR circuit 72 via an inverter. Theoutput terminal of the OR circuit 78 is also connected to a J inputterminal of the JK flip-flop 102 ₁, and the output terminal of the ORcircuit 84 is connected to a K input terminal of the JK flip-flop 102 ₁via the inverter.

Although the first priority encoder 74 and the second priority encoder76 are provided in FIG. 4, only a priority encoder 82 corresponding tothe second priority encoder 76 is provided in this example. That is,while the iterative data searching circuit 21 shown in FIG. 4 is formedby the components from the CAM cell array 26 to the first priorityencoder 74, the iterative data searching circuit 21 shown in thisdrawing is formed by the components from the CAM cell array 26 to thepriority encoder 82 that corresponds to the second priority encoder 76.

The tracing circuits 100 ₁, 100 ₂, . . . , and 100 _(K) can have thesame configuration, and therefore, the tracing circuit 100 _(J) will bedescribed as a representative (J=1, 2, . . . , and K).

The tracing circuit 100 _(J) has substantially the same configuration asthe iterative data searching circuit 21 excluding the CAM cell array 26and the latch 62. More specifically, the tracing circuit 100 _(J) haslatches 106 _(J0) to 106 _(JN), AND circuits 108 _(J0) to 108 _(JN), ANDcircuits 110 _(J0) to 110 _(JN), OR circuits 112 _(J0) to 112 _(JN), anOR circuit 114 _(J), and a priority encoder 116 _(J), which correspondto the latches 66 ₀ to 66 _(N), the AND circuits 68 ₀ to 68 _(N), theAND circuits 70 ₀ to 70 _(N), the OR circuits 72 ₀ to 72 _(N), the ORcircuit 78 and the priority encoder 82 in the iterative data searchingcircuit 21, respectively. Note that, for the tracing circuit 100 _(J),again, the latches 106 _(J0) to 106 _(JN) will be collectively referredto as a latch 106 _(J). Of the AND circuits 108 _(J0) to 108 _(JN), theAND circuits 110 _(J0) to 110 _(JN), and the OR circuits 112 _(J0) to112 _(JN), only the AND circuit 108 _(J1), the AND circuit 110 _(J1) andthe OR circuit 112 _(J1) are shown. However, the respective secondsubscripts (the subscripts indicating the address of the CAM cell row)are not shown.

As shown in FIG. 7-1, the tracing circuit 100 _(J) includes the ORcircuit 114 _(J), the JK flip-flop 102 _(J+1) and the AND circuit 104_(J). An output terminal of the OR circuit 114 _(J) is connected to oneof input terminals of the OR circuit 84. The output terminal of the ORcircuit 114 _(J) is also connected to the J input terminal of the JKflip-flop 102 _(J+1), and an output terminal of the OR circuit 84 isconnected to the K input terminal of the JK flip-flop 102 _(J+1) via aninverter (except in the case where J=K). The output terminal of the ORcircuit 84 is also connected to one of two input terminals of the ANDcircuit 104 _(J), and an output terminal of the JK flip-flop 102 _(J−1)is connected to the other of the two input terminals of the AND circuit104 _(J).

As shown in FIG. 7-2, the iterative data searching apparatus 20 furtherincludes a timing adjusting circuit group 86, a flip-flop group 88, anOR circuit 90, a decoder 92, a flip-flop group 94 and a selector 96.

The timing adjusting circuit group 86 includes AND circuits 118 ₀ to 118_(K) and D flip-flops 120 ₀ to 120 _(K). One of two input terminals ofthe AND circuit 118 ₀ is connected to the output terminal of the ORcircuit 78 in the iterative data searching circuit 21, and the other ofthe two input terminals of the AND circuit 118 ₀ is connected to anoutput terminal of the D flip-flop 120 ₀. A data input terminal of the Dflip-flop 120 ₀ is grounded, and a clock input terminal of the Dflip-flop 120 ₀ is connected to the output terminal of the OR circuit78. One of two input terminals of the AND circuit 118 _(J) is connectedto the output terminal of the OR circuit 114 _(J) in the tracing circuit100 _(J), and the other of the two input terminals of the AND circuit118 _(J) is connected to the output terminal of the D flip-flop 120_(J). The data input terminal of the D flip-flop 120 _(J) is grounded,and the clock input terminal of the D flip-flop 120 _(J) is connected tothe output terminal of the OR circuit 114 _(J) (J=1, 2, . . . , and K).

The flip-flop group 88 includes flip-flops 122 ₀₁ to 122 _(0K), 122 ₁₁to 122 _(1(K-1)), . . . , and 124 _((K-1)1). The flip-flops 122 _(J1) to122 _(J(K-J)) form a (K−J)-stage flip-flop, and an input terminal of theflip-flop 122 _(J(K-J)) is connected to an output terminal of the ANDcircuit 118 _(J), and an output terminal of the flip-flop 122 _(J1) isconnected to input terminals of the OR circuit 90 and the decoder 92(J=1, 2, . . . , and K−1). Note that an output terminal of the ANDcircuit 118 _(K) is directly connected to input terminals of the ORcircuit 90 and the decoder 92.

The flip-flop group 94 includes flip-flops 124 ₀₁ to 124 _(0K), 124 ₁₁to 124 _(1(K-1)), . . . , and 124 _((K-1)1). The flip-flops 124 ₀₁ to124 _(0K) form a K-stage flip-flop, an input terminal of the flip-flop124 _(0K) is connected to the output terminal of the priority encoder 82in the iterative data searching circuit 21, and an output terminal ofthe flip-flop 124 ₀₁ is connected to an input terminal of the selector96. The flip-flop 124 _(J1) to 124 _(J(K-J)) form a (K−J)-stageflip-flop, an input terminal of the flip-flop 124 _(J(K-J)) is connectedto an output terminal of the priority encoder 116 _(J) in the tracingcircuit 100 _(J), and an output terminal of the flip-flop 124 _(J1) isconnected to an input terminal of the selector 96 (J=1, 2, . . . , andK−1). Note that an output terminal of the priority encoder 116 _(K) isdirectly connected to an input terminal of the selector 96.

In the above description, the part formed by the latch 106 _(J), the ANDcircuit 108 ₇, the AND circuit 110 _(J), the OR circuit 112 _(J), the ORcircuit 114 _(J) and the priority encoder 116 _(J) is an example of agenerating circuit, in particular, a J-th expansion generating circuit.The OR circuit 90 is an example of a first output circuit, and theselector 96 is an example of a second output circuit. Although thecomparison result controlling circuit 60 and priority encoder 82 andother components are depicted as part of the iterative data searchingcircuit 21, they function similarly to a tracing circuit. Thus, theiterative data searching circuit 21 can alternatively be defined toexclude the components that function similarly to a tracing circuit,while the excluded components can be defined as an additional tracingcircuit.

Next, an operation of the iterative data searching apparatus 20according to this embodiment will be described with reference to FIGS.8-1 to 8-3. As an example, FIGS. 8-1 to 8-3 show a case where theoriginal data is text data, a character data sequence “ABCXBCDEFY” ispreviously stored in CAM cell rows of addresses “0” to “9”, andcharacter data A, B, C, D, E and F are input in this order as the searchdata, and it is assumed that the number of tracing circuits 100 is five.The latches 62 ₀ to 62 ₉ are shown as ML0 to ML9, the latches 66 ₀ to 66₉ are shown as PS00 to PS09, the latches 106 ₁₀ to 106 ₁₉ are shown asPS10 to PS19, the latches 106 ₂₀ to 106 ₂₉ are shown as PS20 to PS29,and the latches 106 ₅₀ to 106 ₅₉ are shown as PS50 to PS59. It isfurther assumed that if in each of the iterative data searching circuit21 and the tracing circuits 100 ₁, 100 ₂, . . . , and 100 _(J), aplurality of latches PS holds “1”, the priority encoders 82 and 116 ₁,116 ₂, . . . , and 116 _(K) selects and outputs the lowest address.

As shown in FIG. 8-1( a), when character data “A” is first input as thesearch data, the comparison result is “match” in the CAM cell row of anaddress “0”, so that the level held in the latch ML0 is HIGH level.

At this point in time, the levels held in the latches PS00 to PS09 areLOW level, so that all the signals output from the AND circuits 70 ₀ to70 ₉ are at LOW level, and a feedback signal ORFB-0 output from the ORcircuit 78 is also at LOW level.

Since the levels held in the latches PS10 to PS19, . . . , and PS50 toPS59 are LOW level, all the signals output from the AND circuits 110 ₁₀to 110 ₁₉, . . . , and 110 ₅₀ to 110 ₅₉ are at LOW level, and feedbacksignals ORFB-1, . . . , and ORFB-5 output from the OR circuits 114 ₁, .. . , and 114 ₅ are also at LOW level.

Since the feedback signals ORFB-0, ORFB-1, . . . , and ORFB-5 are at LOWlevel as described above, the signal output from the OR circuit 84 is atLOW level, so that all the outputs of the OR circuits 72 ₀ to 72 ₉ areat HIGH level, and the levels of the signals output from the latches ML0to ML9 are held in the latches PS00 to PS09 without change. Thus, onlythe latch PS00 of the latches PS00 to PS09 holds HIGH level, so that thepriority encoder 82 outputs an address “0” as an match address MADR-0(see FIG. 8-1( b)).

In addition, the signal at LOW level output from the OR circuit 78 isinput to the J input terminal of the JK flip-flop 102 ₁, and the signalat HIGH level inverted from the signal at LOW level output from the ORcircuit 84 is input to the K input terminal of the JK flip-flop 102 ₁,so that the level held in the JK flip-flop 102 ₁ is LOW level.

As shown in FIG. 8-1( b), when character data “B” is input as the nextsearch data, the comparison result is “match” in the CAM cell rows ofaddresses “1” and “4”, so that the levels held in the latches ML1 andML4 are HIGH level.

At this point in time, the level held in the latch PS00 is HIGH level,so that the signal output from the AND circuit 70 ₁ is at HIGH level,and the feedback signal ORFB-0 output from the OR circuit 78 is also atHIGH level.

Since the levels held in the latches PS10 to PS19, . . . , and PS50 toPS59 are LOW level, all the signals output from the AND circuits 110 ₁₀to 110 ₁₉, . . . , and 110 ₅₀ to 110 ₅₉ are at LOW level, and thefeedback signals ORFB-1, . . . , and ORFB-5 output from the OR circuits114 ₁, . . . , and 114 ₅ are also at LOW level.

Since the feedback signal ORFB-0 is at HIGH level as described above,the signal output from the OR circuit 84 is also at HIGH level, so thatlogical products of the levels of the signals output from the latchesML0 to ML9 and the signals output from the latches PS in the respectivepreceding stages are held in the latches PS00 to PS09. Thus, only thelatch PS1 of the latches PS00 to PS09 holds HIGH level, so that thepriority encoder 82 outputs an address “1” as the match address MADR-0(see the PS0 field in FIG. 8-2( c)).

The level having been held in the JK flip-flop 102 ₁ is LOW level, andthe signal output from the AND circuit 104 ₁ is also at LOW level, sothat all the outputs of the OR circuits 112 ₁₀ to 112 ₁₉ are at HIGHlevel, and the levels of the signals output from the latches ML0 to ML9are held in the latches PS10 to PS19 without change. Thus, the latchesPS11 and PS14 of the latches PS10 to PS19 hold HIGH level, so that thepriority encoder 116 ₁ outputs an address “1” as the match addressMADR-1 (see the PS1 field in FIG. 8-2( c)).

In addition, the signal at HIGH level output from the OR circuit 78 isinput to the J input terminal of the JK flip-flop 102 ₁, and the signalat LOW level inverted from the signal at HIGH level output from the ORcircuit 84 is input to the K input terminal of the JK flip-flop 102 ₁,so that the level held in the JK flip-flop 102 ₁ is HIGH level.

The signal at LOW level output from the OR circuit 114 ₁ is input to theJ input terminal of the JK flip-flop 102 ₂, and the signal at HIGH levelinverted from the signal at LOW level output from the OR circuit 84 isinput to the K input terminal of the JK flip-flop 102 ₂, so that thelevel held in the JK flip-flop 102 ₂ is LOW level.

As shown in FIG. 8-2( c), when character data “C” is input as the nextsearch data, the comparison result is “match” in the CAM cell rows ofaddresses “2” and “5”, so that the levels held in the latches ML2 andML5 are HIGH level.

At this point in time, the level held in the latch PS01 is HIGH level,so that the signal output from the AND circuit 70 ₁ is at HIGH level,and the feedback signal ORFB-0 output from the OR circuit 78 is also atHIGH level.

Since the levels held in the latches PS11 and PS14 are HIGH level, thesignals output from the AND circuits 110 ₁₁ and 110 ₁₄ are at HIGHlevel, and the feedback signal ORFB-1 output from the OR circuit 114 ₁is also at HIGH level.

Since the levels held in the latches PS20 to PS29, . . . , and PS50 toPS59 are LOW level, all the signals output from the AND circuits 110 ₂₀to 110 ₂₉, . . . , and 110 ₅₀ to 110 ₅₉ are at LOW level, and thefeedback signals ORFB-2, . . . , and ORFB-5 output from the OR circuits114 ₂, . . . , and 114 ₅ are also at LOW level.

Since the feedback signals ORFB-0 and ORFB-1 are at HIGH level asdescribed above, the signal output from the OR circuit 84 is also atHIGH level, so that logical products of the levels of the signals outputfrom the latches ML0 to ML9 and the signal output from the latch PS0 inthe preceding stage are held in the latches PS00 to PS09. Thus, only thelatch PS02 of the latches PS00 to PS09 holds HIGH level, so that thepriority encoder 82 outputs an address “2” as the match address MADR-0(see the PS0 field in FIG. 8-2( d)).

The level having been held in the JK flip-flop 102 ₁ is HIGH level, thesignal output from the OR circuit 84 is at HIGH level, and the signaloutput from the AND circuit 104 ₁ is also at HIGH level, so that logicalproducts of the levels of the signals output from the latches ML0 to ML9and the signal output from the latch PS1 in the preceding stage are heldin the latches PS10 to PS19. Thus, the latches PS12 and PS15 of thelatches PS10 to PS19 hold HIGH level, so that the priority encoder 116 ₁outputs an address “2” as the match address MADR-1 (see the PS1 field inFIG. 8-2( d)).

The level having been held in the JK flip-flop 102 ₂ is LOW level, andthe signal output from the AND circuit 104 ₂ is also at LOW level, sothat all the outputs of the OR circuits 112 ₂₀ to 112 ₂₉ are at HIGHlevel, and the levels of the signals output from the latches ML0 to ML9are held in the latches PS10 to PS19 without change. Thus, the latchesPS22 and PS25 of the latches PS20 to PS29 hold HIGH level, so that thepriority encoder 116 ₂ outputs an address “2” as a match address MADR-2(see the PS2 field in FIG. 8-2( d)).

In addition, the signal at HIGH level output from the OR circuit 78 isinput to the J input terminal of the JK flip-flop 102 ₁, and the signalat LOW level inverted from the signal at HIGH level output from the ORcircuit 84 is input to the K input terminal of the JK flip-flop 102 ₁,so that the level held in the JK flip-flop 102 ₁ is HIGH level.

The signal at HIGH level output from the OR circuit 114 ₁ is input tothe J input terminal of the JK flip-flop 102 ₂, and the signal at LOWlevel inverted from the signal at HIGH level output from the OR circuit84 is input to the K input terminal of the JK flip-flop 102 ₂, so thatthe level held in the JK flip-flop 102 ₂ is HIGH level.

The signal at LOW level output from the OR circuit 114 ₂ is input to theJ input terminal of the JK flip-flop 102 ₃, and the signal at LOW levelinverted from the signal at HIGH level output from the OR circuit 84 isinput to the K input terminal of the JK flip-flop 102 ₃, so that thelevel held in the JK flip-flop 102 ₃ is LOW level.

As shown in FIG. 8-2( d), when character data “D” is input as the nextsearch data, the comparison result is “match” in the CAM cell row of anaddress “6”, so that the level held in the latch ML6 is HIGH level.

At this point in time, the level held in the latch PS05 in the precedingstage of the latch ML6 is LOW level, and the level held in the latchPS02 is HIGH level although the level held in the latch ML3 in thesubsequent stage is LOW level, so that all the signals output from theAND circuits 70 ₀ to 70 ₉ are at LOW level, and the feedback signalORFB-0 output from the OR circuit 78 is also at LOW level.

Since the levels held in the latches PS12, PS15, PS22 and PS25 are HIGHlevel, all the signals output from the AND circuits 110 ₁₀ to 110 ₁₉ and110 ₂₀ to 110 ₂₉ are at HIGH level, and the feedback signals ORFB-1 andORFB-2 output from the OR circuits 114 ₁ and 114 ₂ are also at HIGHlevel.

Since the levels held in the latches PS30 to PS39, . . . , and PS50 toPS59 are LOW level, all the signals output from the AND circuits 110 ₃₀to 110 ₃₉, . . . , and 110 ₅₀ to 110 ₅₉ are at LOW level, and thefeedback signals ORFB-3, . . . , and ORFB-5 output from the OR circuits114 ₃, . . . , and 114 ₅ are also at LOW level.

Since the feedback signals ORFB-1 and ORFB-2 are at HIGH level asdescribed above, the signal output from the OR circuit 84 is also atHIGH level, so that logical products of the levels of the signals outputfrom the latches ML0 to ML9 and the signal output from the latch PS0 inthe preceding stage are held in the latches PS00 to PS09 (see the PS0field in FIG. 8-3( e)). That is, the character sequence no longermatches with the search data at this point, so that the levels held inthe latches PS00 to PS09 are LOW level.

The levels having been held in the JK flip-flops 102 ₁ and 102 ₂ areHIGH level, the signal output from the OR circuit 84 is at HIGH level,and the signals output from the AND circuits 104 ₁ and 104 ₂ are also atHIGH level, so that logical products of the levels of the signals outputfrom the latches ML0 to ML9 and the signals output from the latches PS1and PS2 in the preceding stages are held in the latches PS10 to PS19 andPS20 to PS29. Thus, the latches PS16 and PS26 of the latches PS10 toPS19 and PS20 to PS29 hold HIGH level, so that the priority encoders 116₁ and 116 ₂ output an address “6” as the match addresses MADR-1 andMADR-2 (see the PS1 field and the PS2 field in FIG. 8-3( e)).

The level having been held in the JK flip-flop 102 ₃ is LOW level, andthe signal output from the AND circuit 104 ₃ is also at LOW level, sothat all the outputs of the OR circuits 112 ₃₀ to 112 ₃₉ are at HIGHlevel, and the levels of the signals output from the latches ML0 to ML9are held in the latches PS30 to PS39 without change. Thus, the latchPS36 of the latches PS30 to PS39 hold HIGH level, so that the priorityencoder 116 ₃ outputs an address “6” as a match address MADR-3 (see thePS3 field in FIG. 8-3( e)).

In addition, the signal at LOW level output from the OR circuit 78 isinput to the J input terminal of the JK flip-flop 102 ₁, and the signalat LOW level inverted from the signal at HIGH level output from the ORcircuit 84 is input to the K input terminal of the JK flip-flop 102 ₁,so that the level held in the JK flip-flop 102 ₁ is HIGH level.

The signals at HIGH level output from the OR circuits 114 ₁ and 114 ₂are input to the J input terminals of the JK flip-flops 102 ₂ and 102 ₃,and the signal at LOW level inverted from the signal at HIGH leveloutput from the OR circuit 84 is input to the K input terminals of theJK flip-flops 102 ₂ and 102 ₃, so that the levels held in the JKflip-flops 102 ₂ and 102 ₃ are HIGH level.

The signal at LOW level output from the OR circuit 114 ₃ is input to theJ input terminal of the JK flip-flop 102 ₄, and the signal at LOW levelinverted from the signal at HIGH level output from the OR circuit 84 isinput to the K input terminal of the JK flip-flop 102 ₄, so that thelevel held in the JK flip-flop 102 ₄ is LOW level.

As shown in FIG. 8-3( e), when character data “E” is input as the nextsearch data, the comparison result is “match” in the CAM cell row of anaddress “7”, so that the level held in the latch ML6 is HIGH level.

At this point in time, the levels held in the latches PS00 to PS09 areLOW level, so that all the signals output from the AND circuits 70 ₀ to70 ₉ are at LOW level, and the feedback signal ORFB-0 output from the ORcircuit 78 is also at LOW level.

Since the levels held in the latches PS16, PS26 and PS36 are HIGH level,all the signals output from the AND circuits 110 ₁₀ to 110 ₁₉, 110 ₂₀ to110 ₂₉ and 110 ₃₀ to 110 ₃₉ are at HIGH level, and the feedback signalsORFB-1, ORFB-2 and ORFB-3 output from the OR circuits 114 ₁, 114 ₂ and114 ₃ are also at HIGH level.

Since the levels held in the latches PS40 to PS49 and PS50 to PS59 areLOW level, all the signals output from the AND circuits 110 ₄₀ to 110 ₄₉and 110 ₅₀ to 110 ₅₉ are at LOW level, and the feedback signals ORFB-4and ORFB-5 output from the OR circuits 114 ₄ and 114 ₅ are also at LOWlevel.

Since the feedback signals ORFB-1, ORFB-2 and ORFB-3 are at HIGH levelas described above, the signal output from the OR circuit 84 is also atHIGH level, so that logical products of the levels of the signals outputfrom the latches ML0 to ML9 and the signal output from the latch PS0 inthe preceding stage are held in the latches PS00 to PS09 (see the PS0field in FIG. 8-3( f)).

The levels having been held in the JK flip-flops 102 ₁, 102 ₂ and 102 ₃are HIGH level, the signal output from the OR circuit 84 is at HIGHlevel, and the signals output from the AND circuits 104 ₁, 104 ₂ and 104₃ are also at HIGH level, so that logical products of the levels of thesignals output from the latches ML0 to ML9 and the signals output fromthe latches PS1, PS2 and PS3 in the preceding stages are held in thelatches PS10 to PS19, PS20 to PS29 and PS30 to PS39. Thus, the latchesPS17, PS27 and PS37 of the latches PS10 to PS19, PS20 to PS29 and PS30to PS39 hold HIGH level, so that the priority encoders 116 ₁, 116 ₂ and116 ₃ output an address “7” as the match addresses MADR-1, MADR-2 andMADR-3 (see the PS1 field, the PS2 field and the PS3 field in FIG. 8-3(f)).

The level having been held in the JK flip-flop 102 ₄ is LOW level, andthe signal output from the AND circuit 104 ₄ is also at LOW level, sothat all the outputs of the OR circuits 112 ₄₀ to 112 ₄₉ are at HIGHlevel, and the levels of the signals output from the latches ML0 to ML9are held in the latches PS40 to PS49 without change. Thus, the latchPS47 of the latches PS40 to PS49 hold HIGH level, so that the priorityencoder 116 ₄ outputs an address “7” as a match address MADR-4 (see thePS4 field in FIG. 8-3( f)).

In the operation described above, the feedback signals ORFB-0 to ORFB-K(K=5 in the example described above) output each time character data isinput are output to the decoder 92 via the AND circuits 118 ₀ to 118_(K). In this embodiment, if the feedback signal ORFB from the ORcircuit 84 is set at LOW level, the D flip-flops 120 ₀ to 120 _(K) areset at HIGH level, and the feedback signals ORFB-0 to ORFB-K can passthrough the AND circuits 118 ₀ to 118 _(K). On the other hand, if thelevels of the feedback signals ORFB-0 to ORFB-K are once set at HIGHlevel and then set at LOW level, the levels of the signals input to theclock input terminals of the D flip-flops 120 ₀ to 120 _(K) change fromLOW level to HIGH level, and the feedback signals ORFB-0 to ORFB-Kcannot pass through the AND circuits 118 ₀ to 118 _(K).

The match addresses MADR-0 to MADR-5 that are also output each timecharacter data is input are output to the selector 96.

However, according to this embodiment, the (K−J)-stage flip-flop 122 isprovided prior to the decoder 92 on the path of the feedback signalORFB-J, and the (K−J)-stage flip-flop 124 is provided prior to theselector 96 on the path of the match address MADR-J (J=1, 2, . . . ,K−1), whereas no flip-flop is provided prior to the decoder 92 and theselector 96 on the paths of the feedback signal ORFB-K and the matchaddress MADR-K. As a result, the feedback signals ORFB-0 to ORFB-5 andthe match addresses MADR-0 to MADR-5 do not arrive at the decoder 92 andthe selector 96 at a timing synchronized with the time of input of thecharacter data, which is used as a reference in the operation describedabove, but arrive at the decoder 92 and the selector 96 at a timingshifted by the number of stages of the flip-flop.

Next, an operation of the iterative data searching apparatus 20 withrespect to the timing when the decoder 92 and the selector 96 receivethe signals will be described. Although not shown in FIGS. 8-1 to 8-3,it will be assumed in the following description that the character data“F” shown in FIG. 8-3( f) is the last character data in the charactersequence that matches with the stored data. That is, when the characterdata subsequent to the character data “F” is input, the feedback signalsORFB-0 to ORFB-5 are set at LOW level. The decoder 92 indicates to theselector 96 of the number of any feedback signal ORFB set at HIGH levelof the feedback signals ORFB-0 to ORFB-5, and the selector 96 selectsthe match address MADR for the smallest number from among the matchaddresses MADR for the numbers of which the selector 96 is indicated bythe decoder 92.

First, the point in time when the decoder 92 receives the feedbacksignal ORFB-0 output at the point in time shown in FIG. 8-1( b) from theflip-flop 122 ₀₁ will be considered. At this point in time, the decoder92 receives the feedback signal ORFB-1 output at the point in time shownin FIG. 8-2( c) from the flip-flop 122 ₁₁, the feedback signal ORFB-2output at the point in time shown in FIG. 8-2( d) from the flip-flop 122₂₁, the feedback signal ORFB-3 output at the point in time shown in FIG.8-3( e) from the flip-flop 122 ₃₁, the feedback signal ORFB-4 output atthe point in time shown in FIG. 8-3( f) from the flip-flop 122 ₄₁, andthe feedback signal ORFB-5 (at LOW level) output after the point in timeshown in FIG. 8-3( f) from the priority encoder 116 ₅. In this case, thefeedback signals ORFB-0 to ORFB-4 are at HIGH level, so that aconsolidated ORFB (consolidated feedback signal, abbreviated as C-ORFBhereinafter) output from the OR circuit 90 to the data compressioncontroller 22 is at HIGH level. The decoder 92 informs the selector 96that the feedback signals ORFB-0 to ORFB-4 are at HIGH level, and theselector 96 selects the match address MADR-0 and outputs an address “0”to the data compression controller 22.

Then, the decoder 92 receives the feedback signal ORFB-0 output at thepoint in time shown in FIG. 8-2( c) from the flip-flop 122 ₀₁, thefeedback signal ORFB-1 output at the point in time shown in FIG. 8-2( d)from the flip-flop 122 ₁₁, the feedback signal ORFB-2 output at thepoint in time shown in FIG. 8-3( e) from the flip-flop 122 ₂₁, thefeedback signal ORFB-3 output at the point in time shown in FIG. 8-3( f)from the flip-flop 122 ₃₁, and the feedback signals ORFB-4 and ORFB-5(both at LOW level) output after the point in time shown in FIG. 8-3( f)from the flip-flop 122 ₄₁ and the priority encoder 116 ₅, respectively.In this case, the feedback signals ORFB-0 to ORFB-3 are at HIGH level,so that the consolidated feedback signal C-ORFB output from the ORcircuit 90 to the data compression controller 22 is at HIGH level. Thedecoder 92 informs the selector 96 that the feedback signals ORFB-0 toORFB-3 are at HIGH level, and the selector 96 selects the match addressMADR-0 and outputs an address “1” to the data compression controller 22.

Then, the decoder 92 receives the feedback signal ORFB-0 output at thepoint in time shown in FIG. 8-2( d) from the flip-flop 122 ₀₁, thefeedback signal ORFB-1 output at the point in time shown in FIG. 8-3( e)from the flip-flop 122 ₁₁, the feedback signal ORFB-2 output at thepoint in time shown in FIG. 8-3( f) from the flip-flop 122 ₂₁, and thefeedback signals ORFB-3 to ORFB-5 (all at LOW level) output after thepoint in time shown in FIG. 8-3( f) from the flip-flop 122 ₃₁, theflip-flop 122 ₄₁ and the priority encoder 116 ₅, respectively. In thiscase, the feedback signals ORFB-1 and ORFB-2 are at HIGH level, so thatthe consolidated feedback signal C-ORFB output from the OR circuit 90 tothe data compression controller 22 is at HIGH level. The decoder 92informs the selector 96 that the feedback signals ORFB-1 and ORFB-2 areat HIGH level, and the selector 96 selects the match address MADR-1 andoutputs an address “6” to the data compression controller 22. In theexample shown in FIGS. 8-1 to 8-3, in the case where tracing starts atthe character data “A”, the character sequence no longer matches withthe stored data at this point in time, so that the decoder 92 does notinform the selector 96 of the feedback signal ORFB-0 so that theselector 96 does not select the feedback signal ORFB-0.

Then, the decoder 92 receives the feedback signal ORFB-0 output at thepoint in time shown in FIG. 8-3( e) from the flip-flop 122 ₀₁, thefeedback signal ORFB-1 output at the point in time shown in FIG. 8-3( f)from the flip-flop 122 ₁₁, and the feedback signals ORFB-2 to ORFB-5(all at LOW level) output after the point in time shown in FIG. 8-3( f)from the flip-flop 122 ₂₁, the flip-flop 122 ₃₁, the flip-flop 122 ₄₁and the priority encoder 116 ₅, respectively. In this case, the feedbacksignal ORFB-1 is at HIGH level, so that the consolidated feedback signalC-ORFB output from the OR circuit 90 to the data compression controller22 is at HIGH level. The decoder 92 informs the selector 96 that thefeedback signal ORFB-1 is at HIGH level, and the selector 96 selects thematch address MADR-1 and outputs an address “7” to the data compressioncontroller 22.

Then, the decoder 92 receives the feedback signal ORFB-0 output at thepoint in time shown in FIG. 8-3( f) from the flip-flop 122 ₀₁, and thefeedback signals ORFB-1 to ORFB-5 (all at LOW level) output after thepoint in time shown in FIG. 8-3( f) from the flip-flop 122 ₁₁, theflip-flop 122 ₂₁, the flip-flop 122 ₃₁, the flip-flop 122 ₄₁ and thepriority encoder 116 ₅, respectively. In this case, the feedback signalsORFB-1 to ORFB-5 are all at LOW level, so that the consolidated feedbacksignal C-ORFB output from the OR circuit 90 to the data compressioncontroller 22 is at LOW level.

Therefore, the data compression controller 22 uses, as the matchaddress, the address “7” received from the selector 96 immediatelybefore the consolidated feedback signal C-ORFB is set at LOW level.

Next, an operation of the data compression controller according to thisembodiment will be described.

FIG. 9 is a flowchart showing a process performed in the datacompression controller 22. This process is performed when data to becompressed (original data) is transferred to the data compressioncontroller 22 via the bus 18, and the data compression controller 22 isinstructed by the CPU 12 to compress the original data.

The data compression controller 22 first resets the latches 62 ₀ to 62_(N) and the latches 66 ₀ to 66 _(N) in the comparison resultcontrolling circuit 60 in the iterative data searching apparatus 20(Step 200). Then, initialization is performed to set a match length MLENat “1” and the write address WADR at “0” (Step 202). Then, it isdetermined whether output of the original data to the iterative datasearching apparatus 20 is completed or not (Step 204). If thedetermination result is negative, data on a character C0 correspondingto the leading one character is extracted from the original data assearch data, and the data is output to the iterative data searchingapparatus 20 along with the search instruction SEARCH and the writeaddress WADR (Step 206). In response to this, the iterative datasearching apparatus 20 performs the search operation described above.

Then, the data compression controller 22 determines whether thecharacter sequence match signal C-ORFB output from the iterative datasearching apparatus 20 is set at HIGH level or not (Step 208). In thiscase, since the latches 62 and the latches 66 have been reset inpreceding Step 200, and therefore, the character sequence match signalC-ORFB is maintained at LOW level, the determination result is negative,and the process proceeds to Step 210. Then, the data compressioncontroller 22 determines whether the current comparison operation is thefirst comparison operation on predetermined original data or not (Step210). If the determination result is positive, a processing ofoutputting compressed data in Step 212 is bypassed, and the processproceeds to Step 214. As with the feedback signal ORFB described above,the character sequence match signal C-ORFB is not set at HIGH levelunless two or more successive characters match with the stored data, andtherefore, if a succession of comparison results “not match” occurs, thecharacter searched for in the previous search is output as compresseddata as described later. Thus, there is no data to be output as thecompressed data at this point in time, and therefore, Step 212 is notperformed.

Then, the data compression controller 22 substitutes “1” for the matchlength MLEN (Step 214), and the process proceeds to Step 218. Then, thedata compression controller 22 substitutes data on the character C1searched for in the previous search for the character C2 searched for inthe second previous search and substitutes data on the character C0searched for in the current search for the character C1 searched for inthe previous search (Step 218), and writes the data on the character C0in the CAM cell row corresponding to the current write address WADR (0in the first comparison operation) (Step 220). In practice, the writeprocessing is performed by the address decoder 52 asserting (enabling)the word line of the CAM cell row corresponding to the write addressWADR. Furthermore, the data compression controller 22 increments thewrite address WADR by 1 to provide the next write address WADR (that is,the character data is written in ascending order of the addresses of theCAM cell rows), divides the write address WADR by the size N+1 of theCAM cell array 26, and sets the remainder (Step 222).

Once data are written in all the CAM cell rows in this way, data iswritten in the CAM cell row of an address “0”. Thus, the CAM cell array26 is used as a so-called ring buffer, and an overflow of the CAM cellarray 26 or the like does not occur.

After the processing in Step 222 is performed, the process returns toStep 204. If the result of the determination in Step 204 is negative,the process in Step 206 and the following steps are performed again. InStep 206, data on the character C0 subsequent to the character C1searched for in the previous search is extracted from the original dataas the search data and output to the iterative data searching apparatus20 along with the search instruction SEARCH and the write address WADR.Then, if the result of the determination in Step 208 is negative, theprocess proceeds to Step 210. If the result of the determination in Step210 is negative, the compressed data output processing in Step 212 isperformed.

In this compressed data output processing, as shown in FIG. 10, the datacompression controller 22 determines whether the match length MLEN is 2or not (Step 230). If the result of the previous comparison is “match”,but the result of the second previous comparison is not “match”, thedetermination result is positive, data on the character C2 searched forin the second previous search is output as the compressed data (Step236), data on the character C1 searched for in the previous search isthen output (Step 238), and then the process proceeds to Step 214 in theflowchart shown in FIG. 9.

If the result of the determination in Step 230 is negative, the datacompression controller 22 determines whether the match length MLEN is 1or not (Step 232). If the result of the previous comparison is not“match”, the determination result is positive, data on the character C1searched for in the previous search is output as the compressed data(Step 238), and then the process proceeds to Step 214 in the flowchartshown in FIG. 9.

In the flowchart shown in FIG. 9, if the result of the determination inStep 208 is positive, the match length MLEN is incremented (Step 216),and then, the process proceeds to Step 218. Therefore, no compresseddata is output while the character sequence match signal C-ORFB is atHIGH level.

If the character sequence match signal C-ORFB having been at HIGH levelin the previous comparison operation is changed to LOW level, and theresult of the determination in Step 210 is negative, it means that theend of an iterative character sequence having a length of two or morecharacters is detected, so that the compressed data output processing isperformed in Step 212. In this case, if both the results of the previouscomparison and the second previous comparison are “match”, the matchlength MLEN is incremented to 3 or greater in Step 216 described above,so that the results of the determinations in Steps 230 and 232 are bothnegative, and the process proceeds to Step 234.

Then, the data compression controller 22 determines a compression codefor compressing the iterative character sequence. According to thisembodiment, a compression code comprising a first code that represents apointer that indicates the position of a character sequence that matcheswith the iterative character sequence and a second code that representsthe length of the iterative character sequence is used, the differencebetween the match address MADR and the match length MLEN plus 1(MADR−MLEN+1) is set as the first code and output, and the match lengthMLEN is set as the second code and output (Step 234). As a result, thelength of the compressed data output from the data compressioncontroller 22 is shorter than that of the original data.

When the compression code is output, in order to distinguish between thecompression code and the character data when the compressed charactersequence is decompressed, the data compression controller 22 alsoinserts a code representing a break point between the character data andthe compression code. In this way, each time an iterative charactersequence is found, Step 234 is performed, the found iterative charactersequence is converted into a compression code, and the compression codeis output, thereby removing the redundancy of the original data andcompressing the original data into compressed data.

The process described above is repeated, and when the position in theoriginal data at which data on the character C is extracted reaches theend of the original data, the result of the determination in Step 204 ispositive, and the data compression controller 22 performs the compresseddata output processing again (Step 224). In this case, if the value ofthe match length MLEN is equal to or greater than 3, the compressioncode is output in Step 234. However, if the value of the match lengthMLEN is 2, the data on the character C2 searched for in the secondprevious search is output as the compressed data in Step 236, the dataon the character C1 searched for in the previous search is output as thecompressed data in Step 238, and the process ends. If the value of thematch length MLEN is 1, the data on the character C1 searched for in theprevious search is output as the compressed data in Step 238, and theprocess ends.

Although the pointer that indicates the position of a character sequencethat matches with the iterative character sequence is used as the firstcode of the compression code in this operation example, the distancebetween the position of a character sequence that matches with theiterative character sequence and the position of the iterative charactersequence can also be used, as in the example described above. In thiscase, the data compression controller 22 can recognize the circuit thathas continuously output the feedback signal at HIGH level for thelongest time among the iterative data searching circuit 21 and thetracing circuits 100 ₁, 100 ₂, . . . , and 100 _(K) based on a decodeoutput signal (see FIG. 7-2) from the iterative data searching apparatus20 and use, as the first code, a value obtained by subtracting theposition of the character sequence that matches with the iterativecharacter sequence from the position of the character at which tracingis started in the circuit.

An embodiment of the present inventive subject matter has been describedabove.

As described above, according to this embodiment, to the iterative datasearching circuit 21 that detects character data that matches with inputcharacter data from the CAM cell array 26 and determines whether theinput character data matches with the detected character data as acharacter sequence, the plurality of tracing circuits 100 that make thematching determination for character sequences starting at differentsearch start points shifted in steps of one character is connected. As aresult, a longer character sequence can be efficiently detected from atarget to be searched containing a plurality of character sequenceshaving different lengths containing an identical part, and thecompressibility can be improved.

Although it is assumed in this embodiment that a character sequence iscompressed by replacing a part of the character sequence withinformation on the position and the length of another part of thecharacter sequence, it may be assumed that a search start point forsearching a part of a character sequence is determined based on anotherpart of the character sequence. In that case, it is enough to identifythe circuit for which the number of successive generations of thefeedback signal ORFB at HIGH level is the greatest of the iterative datasearching circuit 21 and the tracing circuits 100 ₁, 100 ₂, . . . , and100 _(K), so that it is not always necessary to determine theconsolidated feedback signal C-ORFB by taking a logical sum of thefeedback signals ORFB or to count the number of successive outputs ofthe consolidated feedback signal C-ORFB.

Although a specific start point previously determined for the circuitfor which the number of successive generations of the feedback signalORFB at HIGH level is the greatest is designated as the search startpoint in this embodiment, the present inventive subject matter is notlimited to this implementation. For example, tracing may be terminatedat the point in time when the number of successive generations of thefeedback signal ORFB at HIGH level exceeds a threshold, any circuit thatis generating the feedback signal at HIGH level at that point in timemay be selected, and the specific start point previously determined forthe selected circuit may be designated as the search start point. Moregenerally, the specific start point previously determined for a circuitthat satisfies a predetermined condition in terms of the number ofsuccessive generations of the feedback signal ORFB at HIGH level may bedesignated as the search start point.

Furthermore, although the specific start points of the iterative datasearching circuit 21 and the tracing circuits 100 ₁, 100 ₂, . . . , and100 _(K) are shifted in steps of one character in this embodiment, thepresent inventive subject matter is not limited to this implementation.It is essential only that the circuits have different specific startpoints, and the specific start points can be shifted in steps of anynumber of characters.

Although an embodiment of the present inventive subject matter has beendescribed above, the technical scope of the present inventive subjectmatter is not limited to the embodiment described above. It is obviousto those skilled in the art that various modifications can be made andvarious alternatives can be used without departing from the spirit andscope of the present inventive subject matter.

1. (canceled)
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 9. An apparatus comprising: aplurality of tracing circuits, wherein a first tracing circuit of theplurality of tracing circuits is configured to, receive a firstindication that a first stored data element of a plurality of storeddata elements matches a first search data element, wherein the firststored data element is associated with a first address; store the firstindication that the first stored data element of the plurality of storeddata elements matches the first search data element; and output anindication of the address associated with the first stored data elementof the plurality of stored data elements; wherein a second tracingcircuit of the plurality of tracing circuits is configured to, receive asecond indication that a second stored data element of the plurality ofstored data elements matches a second search data element, wherein thesecond stored data element of the plurality of stored data elements isassociated with a second address; store the second indication that thesecond stored data element of the plurality of stored data elementsmatches the second search data element; and output an indication of theaddress associated with the second stored data element of the pluralityof stored data elements.
 10. The apparatus of claim 9, wherein theplurality of stored data elements is ordered, wherein one of the secondstored data element of the plurality of stored data elements is orderedsequentially after the first stored data element of the plurality ofstored data elements and the first stored data element of the pluralityof stored data elements is ordered sequentially after the second storeddata element of the plurality of stored data elements.
 11. The apparatusof claim 9, wherein each stored data element of the plurality of storeddata elements corresponds to a row of content addressable memory cellsin an array of content addressable memory cells.
 12. The apparatus ofclaim 9, wherein at least one indication that a stored data elementmatches a search data element is stored in a latch.
 13. The apparatus ofclaim 9, wherein the first tracing circuit of the plurality of tracingcircuits is further configured to: receive a third indication that athird stored data element of the plurality of stored data elementsmatches the first search data element, wherein the third stored dataelement of the plurality of stored data elements is associated with athird address, wherein the third indication is received in parallel withthe first indication; store the third indication that the third storeddata element of the plurality of stored data elements matches the firstsearch data element; and output one of the first address or thirdaddress.
 14. The apparatus of claim 13, wherein the first tracingcircuit configured to output one of the first address or third addressis configured to one of: output the lowest address of the first addressor third address; and output the address, of the first address and thirdaddress, that is nearest to a write address.
 15. The apparatus of claim9 further comprising: a decoder coupled with the plurality of tracingcircuits, the decoder configured to, receive one or more indicationsthat a plurality of sequential stored data elements match a plurality ofsequential search data elements; and output an indication of an addressline of a plurality of address lines; a selector coupled with theplurality of tracing circuits and the decoder, the selector configuredto, receive the indication of the address line of the plurality ofaddress lines; select an address line input based, at least in part, onthe indication of the address line of the plurality of address lines;and output an address corresponding to the selected address line input.16. The apparatus of claim 15 further comprising: a controller coupledwith the plurality of tracing circuits and the selector, the controllerconfigured to, receive the one or more indications that the plurality ofsequential stored data elements match the plurality of sequential searchdata elements; receive the address corresponding to the selected addressline input; determine a count of sequential stored data elements in theplurality of sequential stored data elements; and output an indicationof the address corresponding to the selected address line input and thecount of sequential stored data elements in the plurality of sequentialstored data elements.
 17. The apparatus of claim 16, wherein thecontroller configured to output the indication of the addresscorresponding to the selected address line input and the count ofsequential stored data elements in the plurality of sequential storeddata elements is configured to: generate compressed data by replacing aplurality of original data elements corresponding to the plurality ofsequential search data elements with the indication of the addresscorresponding to the selected address line input and the count ofsequential stored data elements in the plurality of sequential storeddata elements; and output the compressed data.
 18. The apparatus ofclaim 17, wherein the indication of the address corresponding to theselected address line input comprises one of an address corresponding toa row of content addressable memory cells in an array of contentaddressable memory cells, an address corresponding to a location inmemory, and an offset.
 19. An apparatus for determining a longest datasequence of a set of one or more data sequences, the apparatuscomprising: a data searching apparatus configured to determine the setof one or more data sequences, wherein each data sequence of the set ofone or more data sequences matches at least one search data sequence;and a plurality of tracing circuits coupled with the data searchingapparatus, each tracing circuit of the plurality of tracing circuitsconfigured to determine the longest data sequence of the set of one ormore data sequences.
 20. The apparatus of claim 19, wherein the datasearching apparatus comprises: a write buffer; an address decoder; aplurality of match line controllers; a timing controller coupled withthe address controller, the write buffer and the match line controllers;an array of content addressable memory, wherein the array of contentaddressable memory comprises rows of content addressable memory cells,wherein each row of content addressable memory cells stores arepresentation of a data element, wherein each content addressablememory cell of a row of content addressable memory cells are coupledwith a match line, wherein each content addressable memory cell of a rowof content addressable memory cells are coupled with a write line,wherein each write line is coupled with the address decoder, whereineach content addressable memory cell of the content addressable memoryarray is coupled with the write buffer; and a plurality of latches,wherein each latch of the plurality of latches is coupled with a matchline.
 21. The apparatus of claim 19, wherein each tracing circuit of theplurality of tracing circuits comprise: a plurality of signal generatingcircuits, wherein the each signal generating circuit of the plurality ofsignal generating circuits is coupled with a match line; a first OR-gatecoupled with each signal generating circuits of the plurality of signalgenerating circuits; a plurality of latches coupled with each signalgenerating circuit of the plurality of signal generating circuits; and apriority encoder coupled with each latch of the plurality of latches.22. The apparatus of claim 21, wherein each signal generating circuit ofthe plurality of signal generating circuits comprises: a second OR-gatecoupled with a first latch of the plurality of latches and a feedbacksignal line, wherein the first latch of the plurality of latches isassociated with a preceding signal generating circuit of the pluralityof signal generating circuits; a first AND-gate coupled with the secondOR-gate, the match line and a second latch of the plurality of latches,wherein the second latch of the plurality of latches is associated withthe signal generating circuit; and a second AND-gate coupled with thefirst latch of the plurality of latches, the match line and the firstOR-gate.
 23. The apparatus of claim 19 further comprising: a pluralityof match address lines; a first plurality of sets of flip-flops, whereineach set of flip-flops of the first plurality of flip-flops is coupledwith a match address line of the plurality of match address lines; aselector coupled with each match address line of the plurality of matchaddress lines; a plurality of feedback signal lines; a timing adjustmentcircuit coupled with each feedback signal line of the feedback signallines; a second plurality of sets of flip-flops, wherein each set offlip-flops of the second plurality of flip-flops is coupled with afeedback signal line of the plurality of feedback signal lines; and adecoder coupled with each feedback signal line of the plurality offeedback signal lines.
 24. The apparatus of claim 23, wherein the timingadjustment circuit comprises: a plurality of D flip-flops, wherein eachD flip-flop of the plurality of D flip-flops is coupled with a feedbacksignal line of the plurality of feedback signal lines and a sync line;and a plurality of AND-gates, wherein each AND-gate of the plurality ofAND-gates is coupled with a feedback signal line of the plurality offeedback signal lines and a D flip-flop of the plurality of Dflip-flops.
 25. A method comprising: determining a plurality of storeddata sequences that match one or more search data sequences, whereineach of the stored data sequences of the plurality of stored datasequences comprise a plurality of data elements, wherein the stored datasequences are stored in a content addressable memory array; determining,using a plurality of tracing circuits, a longest stored data sequence ofthe plurality of stored data sequences; determining an addressassociated with the longest stored data sequence of the plurality ofstored data sequences; and determining a count of data elements of thelongest stored data sequence of the plurality of stored data sequences.26. The method of claim 25, wherein said determining the plurality ofstored data sequences that match the one or more search data sequencescomprises: determining, using a signal generating circuit, that a firststored data element matches a first search data element; determiningthat a second stored data element matched a second search data element,wherein the second search data element preceded the first search dataelement; and generating a signal, using the signal generating circuit,indicating that the first stored data element and second stored dataelement match the first search data element and the second search dataelement.
 27. The method of claim 25, wherein said determining, using theplurality of tracing circuits, the longest stored data sequence of theplurality of stored data sequences: receiving, at a first tracingcircuit of the plurality of tracing circuits, an indication of a firstdata sequence and a first indication of a second data sequence, whereinthe indication of the first data sequence comprises an indication that afirst search data element matches a first stored data element, whereinthe first indication of the second data sequence comprises an indicationthat the first search data element matches a second stored data element;receiving, at a second tracing circuit of the plurality of tracingcircuits, a second indication of the second data sequence, wherein thesecond indication of the second data sequence comprises an indicationthat a second search data element matches a third stored data element;and indicating that at least one of the first tracing circuit of theplurality of tracing circuits and the second tracing circuit of theplurality of tracing circuits is associated with at least one matchingdata element.
 28. The method of claim 27, wherein said determining theaddress associated with the longest stored data sequence of theplurality of stored data sequences comprises indicating an addressassociated with at least one of the second stored data element and thethird stored data element.